1. Field of Invention
The present invention relates to a semiconductor device and the fabricating method of semiconductor device. More specifically, the present invention relates to the structure of a conductive line and the fabricating method of the same.
2. Description of Related Art
Nowadays, integrated circuit technology is fast advancing, and device minimization and integration are an inevitable trend. While the device size is getting smaller, the size and line width of conductive lines for connecting devices are becoming smaller accordingly. As a result, the difficulty of the fabricating process is increased.
Take the memory fabricated in the silicon wafer as an example, after forming memory cells on the silicon wafer, conductive lines (word line) have to be formed to connect memory cells, so that the memory can work properly.
FIG. 1A is a top view of a flash memory array. The isolation structure 110 of the flash memory array has a stripe layout. The isolation structure 110 is used to define the active area 120. Conductive line 150a (word line) is formed on the active area 120. In the conventional technology, the conductive line 150a is formed by using lithography and etching technology.
FIG. 1B is a cross-sectional view along line P–P′ in FIG. 1A. As shown in FIG. 1B, an isolation structure 110, a tunneling oxide layer 130 and a conductive material layer 140 have been formed in the substrate 100. The isolation structure 110 is between two active areas 120. The tunneling oxide layer 130 and conductive material layer 140 are disposed on the active areas 120. The conductive material layer 140 and its covered active areas 120 have a plurality of semiconductor devices formed thereon (not shown). Next, another layer of conductive material layer (not shown) is formed over the substrate 100 to cover the isolation structure 110 and the conductive material layer 140. Then, the conductive material layer is patterned by using a lithography and etching process, and an opening 165 exposing the isolation structure 110 is formed, so that the conductive lines 150a (word line) connecting memory cell array illustrated in FIG. 1B are fabricated.
However, because of the limitation of the optical design rule of lithography, the method of fabricating the conductive line 150a using lithography and etching process can not be made with smaller size. Moreover, the pattern accuracy of the conductive line 150a is also affected by the accuracy of exposure. In other words, when the exposure mask position or exposure light source angle shifts, the exposure pattern position shifts accordingly, therefore the accuracy of fabricating conductive line 150a position is affected. For example, when the photoresist mask 170 used for fabricating conductive line 150a shifts and dry etching process is used to remove a portion of conductive material layer to form the conductive line 150a, the conductive layer 140 may be damaged or even the tunneling oxide layer 130 (as shown in FIG. 1C) is damaged. As a result, the electrical connection between devices are affected, therefore the devices can not work properly.